faculty Profile

• Completed Ph.D. in the area of Testing of VLSI at St. Joseph’s College of Engineering, Anna University, Chennai August 2020.
• Completed M.Tech. VLSI Design at Bharath Institute of Higher Education & Research, Bharath University in the year 2006.
• Completed B.E. Electronics and Communication Engineering at Bharath Institute of Science and Technology, Madras University in the year 1997.

Professional Memberships

• Member, Institute of Electrical and Electronics Engineers (IEEE)

Teaching Experience

• Working as Associate Professor in the Department of ECE, SVCE since 3rd July 2024 till date.
• Worked as an Associate Professor in the Department of ECE at Prince Shri Venkateswara Padmavathy Engineering College from December 2019 to July 2022.
• Worked as an Associate Professor in the Department of ECE at Velammal Institute of Technology, Ponneri from June 2018 to April 2019.
• Worked as an Associate Professor in the Department of ECE at Madha Engineering College from May 2011 to June 2018.
• Worked as an Assistant Professor in the Department of ECE at Panimalar Engineering College from May 2007 to May 2011.
• Worked as a Senior Lecturer in the Department of ECE at Bharath University from July 2003 to April 2007.
• Worked as a Lecturer in the Department of ECE, Bharath Institute of Science & Technology from July 1999 to June 2003.

Industry Experience

• Worked as a System Engineer at Vansan Systems and Services from June 1997 to June 1999.

Subjects Handled for UG

• Basic Electronics
• Electronic circuits I & II
• Communication Theory and systems
• Satellite communication
• Optical Fiber Communication
• Analog and Digital Communication
• Digital Electronics
• Television & Video Engineering
• Electronic Devices and Circuits
• Linear Integrated Circuits
• VLSI Design
• Microwave Engineering

Subjects Handled for PG

• VLSI Design Techniques.
• Physical design of VLSI Circuits.
• Design of semiconductor memories.
• Testing of VLSI
• Analog Integrated Circuit Design

Research & Consultancy:

• Anna University recognized Supervisor to guide Ph.D/M.S scholars by research (4490012)
• P.Pattunnarajam, G.Naveen Balaji, “Economical SCAN-BIST VLSI Circuits based on reducing testing time by means of ADP,” International Journal of Science, Engineering, and Technology Research (IJSETR), ISSN 2278-7798, Volume 2, Issue 5, May 2013.
• P.Pattunnarajam, J.Srividhya, “A Novel Test-Path Selection Based on Switching Activity and Its BIST Implementation,” International Journal of Advanced Research in Computer Engineering & Technology (IJARCET), ISSN 2278-1323, Volume 3, Issue 5, May 2014.
• P.Pattunnarajam, Reeba Korah, G.Maria Kalavathy, “Test Vector Optimization using POCOFAN- POFRAME Partitioning,” Computers, Materials & Continua, (ISSN 1546-2226) Volume 54, No.3, pp.251-268, June 2018, doi.org/10.3970/cmc.2018.054.251 (WoS & Scopus Indexed).IF-3.21.
• P.Pattunnarajam, Beulah Jackson(2020), “Reduction of Combi-Fault Collapsing using Maxfan Partitioning,” Journal of Computational and Theoretical Nanoscience, Vol.17, Issue 4, pp.1804-181, doi.org/10.1166/jctn.2020.8424.
• P.Pattunnarajam, Reeba Korah, G.Maria Kalavathy(2020).“Analysis of 32×32-bit Parallel Pipeline Multiplier using in-built RTL Testing Approach,” Journal of Computational and Theoretical Nanoscience, Vol.17, Issue 4, pp.1682-1687. http://dx.doi.org/10.1166/jctn.2020.8444.
• Pattunnarajam Paramasivam, Naveenbalaji Gowthaman, Viranjay M. Srivastava, “Design and Analysis of InP/InAs/AlGaAs Based Cylindrical Surrounding Double-Gate (CSDG) MOSFETs with La2O3 for 5-nm Technology,” IEEE Access, Vol. 9, pp.15966-15976, November 2021, doi: 10.1109/ACCESS.2021.3131094 (WoS &Scopus Indexed). I.F-3.367.
• Mercy Theresa M., A. Jesudoss., P. Pattunnarajam., Sudha Rajesh., Jaanaa Rubavathy., A. Raja (2022). CAD Based Automatic Detection of Tuberculosis in Chest Radiograph using Hybrid Method.
• Inderscience International Journal of Engineering Systems Modelling and Simulation, Vol.14, No.4, pp.179-185. doi: 10.1504/IJESMS.2022.10044924. (Scopus &WoS Indexed). I. F-1.1
• Pattunnarajam Paramasivam, Naveenbalaji Gowthaman, Viranjay M. Srivastava, “Design and Analysis of Gallium Arsenide-Based Nanowire using Coupled Non-Equilibrium Green Function for RF Hybrid Applications”, Nanomaterials (MDPI Journals), (ISSN 2079-4991), Volume 13, 959, pp.1-20, March 2023. doi.org/10.3390/nano13060959 (WoS & Scopus Indexed). I.F-5.719.
• Pattunnarajam Paramasivam, Naveenbalaji Gowthaman, Viranjay M. Srivastava (2023), “Parametric Analysis of InGaAs Wafer-based thin body (5nm) Double-Gate MOSFETs for hybrid RF Applications”, Recent Patents on Nanotechnology, (ISSN 1872-2105), Volume 18,(3),pp.334-359. Bentham Science Publications. doi: 10.2174/1872210517666230602095347 (WoS & Scopus Indexed). I.F-2.321.
• Pattunnarajam Paramasivam, Naveenbalaji Gowthaman, Viranjay M. Srivastava (2023), “Analysis of Lanthanum Oxide Based Double-Gate SOI MOSFET using Monte-Carlo Process”, Recent Patents on Nanotechnology, (ISSN 1872-2105). Bentham Science Publications. https://doi.org/10.2174/0118722105273476231201073651 (WoS & Scopus Indexed). I.F-2.321.
• Pattunnarajam Paramasivam, Naveenbalaji Gowthaman, Viranjay M. Srivastava (2023). “Self-Consistent Analysis for Optimization of AlGaAs/GaAs based Heterostructure”, Journal of Electrical Engineering & Technology. Springer, doi.org/10.1007/s42835-023-01721-7) (WoS & Scopus Indexed). I.F-1.528.
• Pattunnarajam, “Enhance Routing Strategy of Wireless Sensor Network based on Fifth Generation Communication Technology”, The Scientific Temper (2023) Vol. 14 (4): pp.1283-1288. (UGC care & WoS Indexed)
• Beulah Jackson, P.Pattunnarajam, M.Bindhu, S.Asha, Vanitha(2023).A triple-band MIMO slot antenna with enhanced resonance for WiMAX, Wi-Fi and WLAN applications. Inderscience International Journal of Engineering Systems Modeling and Simulation, Vol.14, No.3, pp.158-162. doi.org//10.1504/IJESMS.2022.10044364. (Scopus &WoS Indexed). I.F-1.1.
• Pattunnarajam Paramasivam, Naveenbalaji Gowthaman, Viranjay M. Srivastava (2024). “Analytical Modeling of [001] Orientation in Silicon Trigate Rectangular Nanowire using a Tight-Binding Model”, Silicon Journal, Springer. doi.org/10.1007/s12633-024-02864-6 (WoS & Scopus Indexed). I.F-3.4

Patents Published

• Ms.P.Pattunarajam , Dr. M. Mercy Theresa, Dr.J.Joyce Jacob, Dr. Beulah Jackson, Dr. Munish Sabharwal, Dr.Ramesh Kumar,“Sleep Deprivation Detection and Prediction using Machine Learning for Police Officers”, The Patent office Journal (34/2020).
• Dr.P.Pattunarajam, Dr.B.Yamini, Dr.S.Meena, Meenakshi Shunmugam, Dr.A.Jesudoss, Dr.M.Mercy Theresa, “Low Complex Security Mechanism for Implantable Medical Devices against Non-Repudiation Violations”, The Patent Office Journal No.17/2021 dated 23/04/2021.
• Dr. Karpagam. P, Ms. R. Deepika, Mr. Sivakumar Kaliyappan, Ms. A. Haseena, Dr. P. Lavanya, Dr. K. R. Ram Victoria, Dr. P. Pattunnarajam, Dr. P. Abirami, Dr. S. Mohankumar, Dr. Maheswari S, “VLSI-Integrated Hybrid Image Processing Architecture for Biomedical and Smart Agriculture Applications Using AI and Cognitive Radio”, 202541101381 dated 21.10.2025.
• Dr. P. PATTUNNARAJAM, B. ELAKKIYA, “FPGA-Based Intelligent Mobility Nexus: Real-Time Smart Parking and Adaptive Wireless EV Charging System for Sustainable Campus Connectivity”, Application No.202641007182 A dated 24.01.2026.

Journals

• K. Umamaheswari, P. Pattunnarajam, T. Bhargava Ramu, R. Balasubramaniyan, P.S. Gomathi, V. Samuthira Pandi, “Chalcogenide perovskites for next-generation solar cells: Progress, challenges, and future perspectives,” Micro and Nanostructures, 211 (2026) 208526 (WoS & Scopus Indexed). I.F-3.0.

International Conference:
• Rajam, P. P., Theresa, M. M., Slacer, P. P., Priyadharshini, R. I., & Jacob, J. J. (2022, May). “Effective broadside tests using test cube seed generation”, In AIP Conference Proceedings (Vol. 2393, No. 1, p. 020118). AIP Publishing LLC. (Scopus Indexed).
• Priyadharshini, R. I., Slacer, P. P., Benila, A., Theresa, M. M., & Rajam, P. P. (2022, May). “Detection of bridging fault using reduced ordered binary decision diagram”, In AIP Conference Proceedings (Vol. 2393, No. 1, p. 020141). AIP Publishing LLC. (Scopus Indexed).
• Theresa, M. M., Rajam, P. P., Benila, A., Priyadharshini, R. I., & Jacob, J. J. (2022, May). “An intelligent bike safety and surveillance system”. In AIP Conference Proceedings (Vol. 2393, No. 1, p. 020157). AIP Publishing LLC. (Scopus Indexed).
• Priscilla Packia Slacer, R. Indra Priyadharshini, A. Benila, 5. P. Pattunnarajam ,and J. Joyce Jacob(2022,May), “A contemporaneous input vector monitoring BIST Architecture using memory. In AIP Conference Proceedings (Vol. 2393, No. 1, p. 020140). AIP Publishing LLC. (Scopus Indexed).
• J. Joyce Jacob, P.Pattunnarajam, M. Mercy Theresa (2022 May), “IoT Based Automation in the Manhole System,” In AIP Conference Proceedings (Vol. 2393, No. 1, p. 020119). AIP Publishing LLC. (Scopus Indexed).
• P.Pattunnarajam, “EPFC: An Exact Partitioning Fault Collapsing for Combinational Circuits”, International Conference on SMART STRUCTURES AND SYSTEMS (ICSSS 2018), 16th October 2018, Saveetha College of Engineering, Thandalam.
• P.Pattunnarajam, “Smart Cane Illustrator for Visually Challenged”, International Conference on SMART STRUCTURES AND SYSTEMS (ICSSS 2018), 16th October 2018, Saveetha College of Engineering, Thandalam.
• P.Pattunnarajam, “Survey on Comprehensive Healthcare Interoperability with cloud architecture”, International Conference on Smart Structures and Systems (ICSSS 2018), 16th October 2018, Saveetha Engineering College, Thandalam.
• P.Pattunnarajam, “Fault Coverage Based on Functional Broadside Tests using test cube generation”, International Conference in MAGNA on Emerging Engineering Trends (ICMEET2K14), 9th April, Magna College of Engineering, Chennai.
• P.Pattunnarajam, S. Leelavathi, “Standby Leakage power optimization using finite element model in deep submicron ICs”, International Conference on Computational Intelligence and Communication (ICCIC12), 4th July, SKR Engineering College, Chennai.
• P.Pattunnarajam, “Optimization of Stand-by leakage power during the test in deep submicron ICs”, International Conference on Recent Trends in Electrical, Electronics and Embedded systems (RTEE 2012), 10th March, GKM College of Engineering and Technology, Chennai.
• P.Pattunnarajam, “Critical path delay and leakage power reduction during the test in deep submicron ICs”, 2012 IEEE International Conference on Emerging Trends in Science, Engineering, and Technology (INCOSET 2012), 7th December, J.J.College of Engineering and Technology, Trichy. doi:10.1109/INCOSET.2012.6513924 (WoS & Scopus Indexed).

Workshop:

• Attended Short Term course on “Space-Time Processing in Wireless Communications” held on 23rd to 36th February 2005 at TEC, Madurai.
• Participated in Two Days Workshop on “Designing Systems on Programmable Chip” held on 23 to 25th December 2005 at NIT, TIRCHY.
• Participated in Two Days Workshop on “Analog IC Design” held on 14th & 15th September 2012 at MIT campus, Chennai
• Participated in Two Days Workshop on “VLSI Mems & Integration” held on 9th &10th December 2011 at VIT, Chennai.
• Participated Two days National level workshop on “VLSI Design & Nanotechnology” on 7th and 8th November 2012 at SA Engineering College , Chennai.
• Participated in One Day Workshop on “How to Write Research Papers for Refereed Journals” held on 24th January 2015 at Sairam Institute of Technology, Chennai.
• Participated in Five Days short term training Programme on “VLSI and Embedded Systems for IOT Applications” held on 30th October to 3rd November 2018 at SRM University, Chennai.
• Participated Technical Webinar on “Machine Learning using Python” held on 2nd July 2020 at Saveetha Engineering College.
• Participated Technical Webinar on “Signal Processing based on Time Frequency Domain” held on 14th July 2020 at IEEE Signal Processing Society association with MES College of Engineering, Pune-01.
• Presented Online Workshop for Prefinal and Final year students on “How to Write Journal Paper” held on 16th October 2021 at Saveetha Engineering College.
• Attended a one-day workshop on “Data Visualization and Business Intelligence Using Tableau” conducted by Sri Venkateswara College of Engineering, Sriperumbudur, on 26th June 2025.
• Participated in a three-day workshop on “AI-Enabled Semiconductor IC Design and Performance of Nanoscale Devices” under AICTE–VAANI, conducted in Tamil language by Vellore Institute of Technology, Chennai, from 19th to 21st November 2025.
• Attended a five-day’s workshop on “FDP on VLSI Design Flow from RTL to GDSII” on 9th to 13th March 2026 conducted under E & ICT Academy – Phase II, an initiative of the Ministry of Electronics & Information Technology (MeitY), Government of India at Rajalakshmi Institute of Technology, Chennai.

FDP:

• Participated in Five days FDP on “Recent developments in Communication, Networking & Research Opportunities” held on 23rd to 27th June 2020 at Srinivas Institute of Science & Technology, Chitoor.
• Attended Online FDP on “ASIC Design for Driving Digital Innovations in Next-Gen Platform” held on 23rd to 27th August 2021 at Acharya Institute of Technology, New Delhi, ATAL Academy.
• Attended Online FDP on “NanoElectronics and RF Engineering ” held on 6th to 10th Setember 2021 at SRM Institute of Management and Technology, ATAL Academy.
• Attended online FDP on “The Trends of Research and Development of Electronics and Communication Area in Electronics and Communication Engineering” held on 17th to 21st Jan 2022 at NIT, Manipur.
• Attended Online FDP on “Low Power VlSI & its Industry Trends” held on 18th to 23rd April 2022 at Sanskriti School of Engineering.
• Attended ATAL FDP on “Semiconductor Device Design from RTL to GDSII” held on 18th to 23rd Dec 2023 at Veltech Rangarajan Dr.Saguntala R&D Institute of Science & Technology.
• Participated in a six-day ATAL FDP on “Industrial Applications of Embedded Systems and IoT” conducted by Rajalakshmi College of Engineering, Thandalam, from 22nd to 28th August 2024.
• Participated in an ATAL FDP on “IoT in Healthcare: Transforming Patient Care and Management” organized by Sri Venkateswara College of Engineering, Sriperumbudur, from 9th to 14th December 2024.
• Attended an FDP on “Unlocking the Potential of AI in VLSI System Design and IC Packaging” conducted by BV Raju Institute of Technology, from 16th to 21st December 2024.
• Attended a six-day ATAL FDP on “AI in the Development of Next-Generation Semiconductor Materials” organized by Kings Engineering College, Sriperumbudur, from 23rd to 28th June 2025.

Certified Courses Completed:

• Completed 12 weeks certified NPTEL online course on “Digital VLSI Testing” conducted by IIT, Kharagpur and received ELITE certificate during July-October 2024.
• Successfully completed 8 weeks certified NPTEL online course on “Hardware Modeling Using Verilog” conducted by IIT Madras during the year July-Dec 2025.
• Completed 12 weeks certified NPTEL online course on “VLSI Design Flow: RTL to GDS” conducted by IIIT, Delhi and received ELITE certificate during July-October 2025.
• Successfully completed the 12 weeks certified NPTEL online course on “Semiconductor Devices for Next Generation Field Effect Transistors (More than Moore): A Physics Perspective” conducted by IIT Madras during the year Jan-April 2025.
• Successfully Completed Certificate course on “FPGA signal Processing Systems” conducted by IIT Madras during Jan-April 2026.

Books reviewed/published:

• Reviewed the manuscript titled “A hybrid Encoding Strategy for Classification of Medical Imaging Modalities Journal of Ambient Intelligence and Humanized Computing” for Journal of Ambient Intelligence and Humanized Computing, Springer 2020.
• Published textbook in the title “ARTIFICIAL INTELLIGENCE FOUNDATION FOR VLSI APPLICATION AND DESIGNS”, Scientific International Publishing House (SIPH), January 2022.
• Reviewer for National Conference on Computational Intelligence and Communication Networks, (NCCICN’21) at Sathyabama University, Springer 2022.
• Reviewed the manuscript titled “Electrical Noise, Temperature Fluctuations and Sensitivity of a Vertical TFET based Biosensor with Dielectric Pocket under the influence of Interface Trap Charges”, Journal of Discover Electronics, Springer, 24th March 2026.
• Reviewed the manuscript titled “Decision on “GaSb/Si Heterojunction Segmented-Channel Vertical-TFET for High- Sensitivity Gas Sensing in Biomedical and Industrial Environments” for Journal of Applied Physics A, Springer ON 26th April 2026.

• Faculty Advisor for Batch 2022-2026
• NPTEL Coordinator
• IQAC Coordinator
• TNSCST Incharges
• Research Objective Coordinator
• Faculty Feedback Incharges
• Student activities Incharges

• Certified and won cash award for producing above 90% results on Television Engineering subjects for UG-IV ECE during 2007-08 odd semester.
• Certified for producing above 90% results on Electronic Circuits-I subjects for UG-II ECE during 2011-12 odd semester.
• Certified for completing 8 weeks certified NPTEL online course on “CMOS Digital VLSI Design” conducted by IITM, Roorkee in April 2019.
• Organized Blood camp and donated blood in Velammal Institute of Technology 2019.
• Reviewer for Journal of Ambient Intelligence and Humanized Computing, Springer 2020.
• Completed Certificate course on “AI for Everyone” offered by COURSERA.
• Reviewer for National Conference on Computational Intelligence and Communication
• Certified for completing 8 weeks NPTEL online course on “CMOS Digital VLSI Design” conducted by IITM, Roorkee in April 2022 and awarded an ELITE certificate and secured 68%.
• Networks, (NCCICN’21) at Sathyabama University, Springer 2022.
• Conference Session Chair in an “IEEE International Conference on Smart Structures and Systems” ICSSS 2022 at Saveetha Engineering College.
• Reviewer for the Journal National Academy Science Letters, Springer 2025.
• Honoured as an Academic Editor for the textbook titled “Microelectronics Beyond Scaling – Advanced Transistor Design and Emerging Technologies”, Intechopen Publisher, United Kingdom, 2026.
• Reviewer for the Journal of Discover Electronics, Springer 2026.
• Reviewer for the Journal of Applied Physics A, Springer 2026.