|Areas of Interest||VLSI Design, Verification and Testing, Computer Architecture, Digital Signal Processing|
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|Email Id (Personal)||firstname.lastname@example.org|
- PhD “Development of New Preprocessing Techniques for Binary Decision Diagram Construction and Reversible Circuit Optimization”, Faculty of Information and Communication Engineering, Anna University, Chennai (2016)
- M.E (Applied Electronics)(2004),College of Engineering, Anna University,Chennai.
- B.E (ECE)(1991),The Indian Engineering College, Madurai Kamaraj University.
- Working at SVCE since June 2004.
- Total Teaching Experience as on June 2017: 20 years,6 months
- Industry Experience: 1 year,10 months
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®Sri Venkateswara College of Engineering
- S.R.Malathi, Akshaya Venugopal, Pavithra Sarathy, “A Cost Effective Design of Reversible Single Precision Floating Point Multiplier”, International Journal of Research in Computer and Communication technology, IJRCCT, ISSN 2278-5841, Vol 2, Issue 1, January 2013, pp 26 – 31.
2. S.R.Malathi, R.Ramya Asmi, “Reduction of bus transition for compressed code systems”, International Journal of VLSI design & Communication Systems (VLSICS) Vol.4, No.1, February 2013, pp 123-134. DOI : 10.5121/vlsic.2013.4110
3. M. Subash, S.R.Malathi, “Using Multiple Viewpoint Templates for Target Detection In High Resolution Images”, International Journal of Engineering Research & Technology (IJERT) ISSN: 2278-0181, Vol. 2 Issue 6, June – 2013, pp 704 – 708. DOI : IJERTV2IS60306
4. SM. Nithyabhavani & S. R. Malathi, 2014 July “Rearrangement of Pixels and Patches to Remove Noise in Color Images and to Restore the Missing Pixels in it by Permuting its Pixels and Patches”, International Journal of Engineering Research & Technology (IJERT), Vol. 3 Issue 7, pp. 1686 to 1693, ISSN: 2278-0181.
5. E.Nandhini, & S.R.Malathi, 2014 July “Location of Fovea Centralis in Digital Fundus Images using Adaptive Thresholding Method”, International Journal of Pharma and Bio Sciences, 5(3):(B) 590-600 ISSN:0975-6299.(Annexure II) (Available in UGC Approved Journal List, Scopus Indexed, Indian Citation Indexed(ICI))
6. Malathi, S. R., & Sakthivel, P. 2014, “A New Preprocessing Method for Efficient Construction of Decision Diagrams”,IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences,Vol.E97-A, No.2, pp. 624-631, ISSN:0916-8508 (Annexure I) (Available in UGC Approved Journal List, Web of Science Indexed, Scopus Indexed, Indian Citation Indexed(ICI))
7. Malathi, S. R., and Sakthivel, P. 2014, “A New Optimization Method for Reversible Circuits using BDD”, International Journal of Applied Engineering Research, Vol.9, No. 21, pp. 4889-4894, ISSN 0973-4562 (Annexure II) (Available in UGC Approved Journal List, Scopus Indexed, Indian Citation Indexed(ICI))
8.Malathi, S. R., and Sakthivel, P. 2015, “An Efficient Method for Computing Total Autocorrelation over Shared Binary Decision Diagram”, International Journal of Applied Engineering Research, Vol.10, No. 11, pp. 29773-29782, ISSN 0973-4562 (Annexure II) (Available in UGC Approved Journal List, Scopus Indexed, Indian Citation Indexed(ICI))
9. Nadar James Francis Joseph Roy, S.R.Malathi, April 2017 “Folded Architecture for Adaptive Digital Filter”, International Journal of Innovative Research in Computer and Communication Engineering, Vol.5, Spl.Issue-3 pp.257-265, eISSN 2320-9801
1. Dr.D.Ebenezer, O.Uma Maheshwari, S.R.Malathi, “A New FMH Filter Algorithm for removing Impulse Noise”, in IEEE sponsored International Conference on Signal Processing and Communications (SPCOM 04), IISc, Bangalore, Dec.11-14, 2004, pp 453-456.
2. S.Suvena, S.R.Malathi, “Identity Based Proxy Encryption and Group Rekeying Strategy for Secure Multicast”, in ISTE sponsored National Conference on Research Opportunities and Challenges in IT (NCRC’07), Sai Ram Engineering College, Chennai, April 4, 2007, pp 24-29.
3. Ramya Asmi. R, S.R.Malathi, “Reduction of bus transition for compressed code systems”, in National Conference on VLSI DESIGN & IMAGE PROCESSING (NCVLSI’11), pp.128-133, 2011.
4. Arun Prasad.R, S.R.Malathi, “Limiting Wakeup Frequency in a Mesh Sensor Network using Optimal Wakeup Scheduling Algorithm”, in the National Conference on Emerging Issues in Computer Applications (EICA’11), on 10th February 2011.
5. R.Manikandan,S.R.Malathi, “Implementation of Scalable Encryption Algorithm using Reversible Logic,” in the International Conference on Electrical and Electronics Engineering (ICEEE-2012), Coimbatore, 22nd April 2012.
6. K.Malathi, S.R.Malathi, “An Efficient Bufferless Routing using Unicast based Multicast Method,” in the International Conference on Electrical and Electronics Engineering (ICEEE-2012), Coimbatore, 22nd April 2012.
7. AR Manoj Amog Surya, S.R.Malathi, “Extraction and Analysis of Diabetic Retinopathy Features from Color Fundus Images”, in the National Conference on Innovations and Research Areas in Computer Applications (NCIRACA ’13), SKR Engineering College, Chennai, 29th June 2013.
8. M.Nithyabhavani, S.R.Malathi, “Application of Linear and Non-Linear Filters to Patch Based Image Processing Technique,” International conference on Emerging Trends in Science, Engineering and Technology (ICETSET-2014), Jerusalem College of Engineering, Chennai, 18-19, April 2014.
Short Term Courses Attended:
- Short Term Course under QIP on “Digital VLSI Front End Design”, conducted by IIT, Madras form 06-09-2004 to 10-09-2004.
2. AICTE-ISTE Short term course on “Advanced Aspects of VLSI Design Automation”, conducted by IIT, Madras from 13-09-2004 to 17-09-2004
3. AICTE-ISTE short term training programme on “Nano Computing”, conducted by SVCE, Pennalur from 22-11-2004 to 03-12-2004.
4. IEEE sponsored Faculty Development Programme on “Computer Organisation and Architecture”, conducted by IIT, Madras on 14-15 Oct, 2006.
5. Anna University sponsored, Faculty Development Programme on “Digital Communication”, conducted by SVCE during 03-15 Dec 2007.
6. Faculty Development Programme on “VLSI Design”, conducted by College of Engineering, Guindy, Anna University, from 24th to 30th May 2008.
7. AICTE sponsored Faculty Development Programme on “Hardware Verification Techniques”, KCG College of Technology, Chennai, from 25-Nov-2013 to 8-Dec-2013.
8. Information Security Education and Awareness – Faculty Development Programme (ISEA-FDP), on “Architectural Aid to Secure System Design”, sponsored by Department of Electronics and Information Technology (DeitY), Govt. of India, conducted at IIT-Madras, from 14th to 18th December 2015.
9.Successfully completed, Ministry of HRD, Govt. of India funded, NPTEL course on “VLSI Design Verification and Test” conducted from July-October 2016.
10.Successfully completed, Ministry of HRD, Govt. of India funded, NPTEL course on “Digital VLSI Testing” conducted from January-April 2017 with ELITE Certification.
- Symposium on “DSP Emerging Trends and Opportunities”, jointly conducted by TI, SANDS and IEE on 9th Jan 2004.
2. Workshop on “Modern Computer Architecture”, conducted by Microcode on 4th Aug 2004.
3. “Multi Core Workshop” conducted by IIT, Madras and Intel Higher Education Programme on 11th Nov 2006.
4. “Machintosh Products Workshop MPW 2008”, organized by Department of CSE and Datalogics India Pvt.Ltd., on 29th September 2008.
5. One day workshop on “Ansoft High Frequency Applications”, conducted by the Department of ECE, Anna University and ACTIVE, Bangalore on 26th February 2010.
6. Two Day Workshop on “Innovation through effective thinking”, conducted by VLSI Society of India, at Texas Instruments , Bangalore on 5-6,March 2010.
7. Two Day Workshop on “Research Methods”, conducted by National Institute of Technology, Tiruchirappalli, on 5-6, August 2010.
8. One day workshop on “Java/J2EE Technologies”, conducted by Department of CSE, SVCE, on 28th December, 2010.
9. Two days workshop on “FPGA Design Flow”, Conducted by Department of ECE, SVCE, on 3rd and 4th February, 2011.
10. Two days workshop on “Embedded System Design on FPGA”, conducted by Department of ECE, M.A.M College of Engg and Technology, Trichy on 11th and 12th March 2011.
11. ACM Chennai Research Seminar on “Formal Methods for Specification and Verification”, conducted by ACM India Chennai Professional Chapter, on July 9, 2011, at Chennai Mathematical Institute.
12. Workshop on “Image Processing Framework using FPGA,” conducted by EEE Dept, SVCE and Enixs Technology India Pvt Ltd. On Feb 03-04, 2012.
13. Workshop on Graph Algorithms (WGA – 2012), conducted by Indian Statistical Institute, Chennai Centre, on March 30-31, 2012.
14. Workshop on “Graph Theory – Introduction and Applications”, conducted by the Department of Applied Mathematics, SVCE, on 3rd November 2012.
15. Workshop on “Linux System Administration”, conducted by the Department of Computer Science and Engineering, SVCE, on 18-19th December, 2013.
16. Workshop on “Avoiding the Risks of Plagiarism in Research Publication”, conducted by CSI Chennai Chapter, IEEE Computer Society Madras Chapter and IEEE Professional Communication Society Madras Chapter, Chennai, on 3rd May 2014.
17.Workshop on “Analog Custom IC Design using Cadence EDA” conducted by the Department of ECE, SVCE, on 19th and 20th August 2016.
Special Lectures Delivered:
- Delivered a special lecture on “VLSI and Microelectronics”, on 26th Nov 2004, in the ISTE sponsored “Short Term Training Programme on Nano Computing”, organized by CSE department , Sri Venkateswara College of Engineering.
2. Delivered a lecture on Basic Processing Unit in Computer Architecture at SKR Engineering College, Nazarethpet, on 22nd March 2008.
3.Delivered a special lecture on “Introduction to VHDL”on 08-08-2016 in the Department of Electrical and Electronics, Velammal Engineering College, Chennai-600066.
4. Delivered a special lecture on “Power optimization strategies for Processes and CPU”, for the Faculty Development Training Program in Embedded and Real time systems on 16-6-2017.
Technical Workshops Organized:
- Two Day Tutorial on “DSP Applications using MATLAB” on 24/ 09/ 2005 and 26/ 09/ 2005
2. Two Day National Workshop on “Natural Language Processing (NWNLP 06)” on 20-21, April 2006
3. Two Day National Workshop on “VLSI Systems (NWVLSIS ’09)”, on 13th-14th March, 2009
ISO-RO In-charge, Research Coordinator-1, Module Coordinator.